The present invention relates to a semiconductor memory device, and more particularly to a pumping voltage sensing circuit capable of controlling a pumping voltage to be stably generated in a low voltage environment and a method of sensing the pumping voltage.
Semiconductor memory devices are used in various fields, one of which is storing various data. Since the semiconductor memory devices are used for various portable apparatuses such as desktop computers and notebook computers, the semiconductor memory devices are developed to meet various requirements such as larger capacity, higher operating speed, smaller size, and lower power consumption.
As a method of designing a semiconductor memory device to operate with low power consumption, a technology for minimizing the consumption of current in the core area of a semiconductor memory device is provided. The core area includes memory cells, bit lines, and word lines and is designed in accordance with an extremely fine design rule. Therefore, in order to design an extremely fine semiconductor memory device that performs a high frequency operation, a power source voltage is basically required to be very low. A power source voltage of no more than 1.5 volts is currently applied.
On the other hand, the semiconductor memory device generates internal voltages using an external power source voltage of no more than 1.5 volts. One of the methods of generating the internal voltages is to generate internal electric potentials higher than the external power source potential or lower than ground potential using a charge pump.
Among the internal voltages generated by charge pumping, a high level pumping voltage, i.e., a boost voltage VPP, and a low level pumping voltage, i.e., a back bias voltage VBB, are most commonly used for a semiconductor memory device such as DRAM. The boost voltage VPP is applied to a gate of a cell transistor, i.e., a word line, as a higher potential than a power source voltage VCC or VDD in order to access a cell. In order to prevent data stored in the cell from being lost, the back bias voltage VBB lower than a ground voltage VSS is applied to a bulk BULK of the cell transistor.
The boost voltage VPP that is higher than a supplied power source and that is mainly supplied to word lines will be described.
FIG. 1 is a block diagram of an internal voltage generating circuit of a conventional semiconductor memory device.
As described above, the internal voltage generating circuit for generating a pumping voltage VPP includes a voltage sensing circuit 10, a ring oscillator 20, a control signal generator 30, and a pumping circuit 40. The voltage sensing circuit 10 compares a reference voltage VREF with a fed-back pumping voltage VPP to sense the level of the pumping voltage VPP so that the pumping voltage can maintain a constant voltage level. The ring oscillator 20 generates a clock signal OSC for generating the pumping voltage VPP based on an output signal VPPE of the voltage sensing circuit 10. The control signal generator 30 generates control pulses for controlling the pumping circuit 40. The pumping circuit 40 generates the pumping voltage VPP by boosting an external voltage VDD in response to an output signal of the control signals generator 30.
The voltage sensing circuit 10 compares the reference voltage VREF with the fed-back pumping voltage VPP and outputs a pumping voltage enable signal VPP_EN when the fed-back pumping voltage is lower than the reference voltage VREF. The pumping voltage enable signal VPP_EN enables the ring oscillator 20 and the clock signal OSC generated by the oscillator 20 is supplied to the control signal generator 30. The control signal generator 30 outputs the control pulses in response to the clock signal OSC. The pumping circuit 40 is enabled by the control pulses to generate the pumping voltage VPP by boosting the power source voltage VDD.
That is, the pumping circuit 40 is enabled when the fed-back pumping voltage VPP is lower than the reference voltage VREF and generates the pumping voltage VPP by boosting the power source voltage VDD. As described above, the pumping circuit 40 operates based on the detection value of the voltage sensing circuit 10 for comparing the fed-back pumping voltage with the reference voltage to sense a voltage level.
FIG. 2 is a schematic circuit diagram of the voltage sensing circuit in FIG. 1.
The voltage sensing circuit 10 includes a voltage dividing unit 12, a comparing unit 14, and a buffering unit 16.
The voltage dividing unit 12 includes a plurality of resistors R1 to R4 serially connected between the fed-back pumping voltage VPP and the ground voltage VSS. The fed-back pumping voltage VPP is divided by the ratios of the plurality of resistors R1 to R4 to generate a divided voltage VPP_REF.
The comparing unit 14 includes three NMOS transistors N1 to N3 and two PMOS transistor P1 and P2 to compare the divided voltage VPP_REF obtained by dividing the fed-back pumping voltage VPP with the reference voltage VREF. That is, the divided voltage VPP_REF is input to the gate terminal of a first NMOS transistor N1 and the reference voltage VREF is input to the gate terminal of a second NMOS transistor N2. Then, the source terminals of the two NMOS transistors N1 and N2 are connected to the drain terminal of a third NMOS transistor N3 that receives a bias voltage VBIAS through the gate terminal thereof. The source terminal of the third NMOS transistor N3 is connected to the ground voltage VSS. Then, the drain terminals of the NMOS transistors N1 and N2 are connected to the PMOS transistors P1 and P2 that constitute a current mirror. That is, the current of one terminal of the current mirror is controlled by the first NMOS transistor N1 as a switching element and the current of the other terminal of the current mirror is controlled by the second NMOS transistor N2 as a switching element. The output terminal of the comparing unit 14 is provided between the second PMOS transistor P2 that constitutes the current mirror and the second NMOS transistor N2 that receives the reference voltage.
The buffering unit 16 includes an inverter IV1 connected to the output terminal of the comparing unit 14 to buffer the comparison result of the comparing unit 14.
The conventional voltage sensing circuit having the above structure operates as follows.
The fed-back pumping voltage VPP is divided by the resistor R1 to R4 in the voltage dividing unit 12. The divided voltage VPP_REF is compared with the reference voltage VREF by the comparing unit 14. When the divided voltage VPP_REF is lower than the reference voltage VREF, the output of the comparing unit 14 is in a logic low level and the logic low level signal is inverted by the buffering unit 16 to output a logic high level signal. At this time, the voltage sensing circuit 10 outputs the pumping voltage enable signal VPP_EN for generating the pumping voltage. The pumping voltage enable signal VPP_EN enables the ring oscillator 20 to generate the pumping voltage VPP.
To the contrary, when the divided voltage VPP_REF is higher than the reference voltage VREF, the output of the comparing unit 14 is in a logic high level and the logic high level signal is inverted by the buffering unit 16 to output a logic low level signal. At this time, the voltage sensing circuit 10 controls the pumping voltage enable signal VPP_EN to be disabled. That is, the ring oscillator 20 is no longer driven.
On the other hand, as described above, the design environment of the semiconductor memory device is changed for the semiconductor memory device to be capable of operating at a low voltage. That is, a power source voltage of no more than 1.5 volts can be applied.
When the supplied power source voltage VDD is reduced to less than 1.5 volts, in the structure of the comparing unit 14, a node voltage between the first PMOS transistor P1 and the first NMOS transistor N1 is reduced to turn on the first PMOS transistor P1. Therefore, the first NMOS transistor Ni can be turned on only when the node voltage between the first and the third NMOS transistors NI and N3 is reduced.
However, in the conventional voltage sensing circuit, a ground voltage (0 volt) is used as the source voltage of the third NMOS transistor N3 in an environment where the power source voltage VDD is reduced. Therefore, the third NMOS transistor N3 falls into a triode area so that the third NMOS transistor N3 does not operate as the current source.